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M48T212A
3.3V TIMEKEEPER(R) CONTROLLER
PRELIMINARY DATA
s
CONVERTS LOW POWER SRAM into NVRAMs YEAR 2000 COMPLIANT (4-Digit Year) USES SUPER CAPACITOR or LITHIUM BATTERY (User Supplied) BATTERY LOW FLAG INTEGRATED REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WATCHDOG TIMER WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T212A: 2.7V VPFD 3.0V MICROPROCESSOR POWER-ON RESET PROGRAMMABLE ALARM OUTPUT ACTIVE in the BATTERY BACKED-UP MODE
4 A0-A3 A E EX W G WDI RSTIN1 RSTIN2 X0 XI M48T212A IRQ/FT RST E1CON E2CON VCCSW VOUT
s s
s s
44 1
SOH44 (MH)
s
s s
s s
Figure 1. Logic Diagram
VCC VCAP
DESCRIPTION The M48T212A is a self-contained device that includes a real time clock (RTC), programmable alarms, a watchdog timer, and two external chip enable outputs which provide control of up to four (two in parallel) external low-power static RAMs. A built-in 32.768 kHz oscillator (external crystal controlled) is used for the clock/calendar function. Access to all TIMEKEEPER functions and the external RAM is the same as conventional byte-wide SRAM. The 16 TIMEKEEPER Registers offer Century, Year, Month, Date, Day, Hour, Minute, Second, Control, Calibration, Alarm, Watchdog, and Flags. Externally attached static RAMs are controlled by the M48T212A via the E1CON and E2CON signals (see Table 4). Automatic backup and write protection for an external SRAM is provided through VOUT, E1CON and E2CON pins. (Users are urged to insure that voltage specifications, for both the controller chip and external SRAM chosen, are similar).
8 DQ0-DQ7
VSS
VBAT-
AI03047
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M48T212A
Figure 2. SOIC Connections Table 1. Signal Names
A0-A3 DQ0-DQ7 XO Address Inputs Data Inputs/Outputs Oscillator Output Oscillator Input Reset 1 Input Reset 2 Input Reset Output (Open Drain) Watchdog Input Bank Select Input Chip Enable Input External Chip Enable Input Output Enable Input Write Enable Input RAM Chip Enable 1 Output RAM Chip Enable 2 Output Int/Freq Test Output (Open Drain) VCC Switch Output Supply Voltage Output Super Capacitor Input Battery Ground Pin (optional) Supply Voltage Ground Not Connected internally
RSTIN1 RSTIN2 RST NC XO XI NC NC A NC NC NC A3 A2 A1 A0 WDI E2CON DQ0 DQ1 DQ2 VSS
44 1 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 34 11 M48T212A 33 12 32 13 31 14 30 15 29 16 28 17 27 18 26 19 25 20 24 21 23 22
AI03048
VCC VOUT VCCSW IRQ/FT EX NC NC NC NC NC G W VBAT- NC E E1CON DQ7 DQ6 DQ5 DQ4 DQ3 VCAP
XI RSTIN1 RSTIN2 RST WDI A E EX G W E1CON E2CON IRQ/FT Vccsw VOUT VCAP VBAT- VCC VSS NC
The lithium energy source (or super capacitor) used to permanently power the real time clock is also used to retain RAM data in the absence of VCC power through the VOUT pin. The chip enable outputs to RAM (E1CON and E2CON) are controlled during power transients to prevent data corruption. The date is automatically adjusted for months with less than 31 days and corrects for leap years. The internal watchdog timer provides programmable alarm windows. The nine clock bytes (Fh - 9h and 1h) are not the actual clock counters, they are memory locations consisting of BiPORTTM read/write memory cells within the static RAM array. Clock circuitry updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7h con2/20
tains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the Watchdog Steering bit (WDS). Bytes 6h-2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 1h contains century information. Byte 0h contains additional flag information pertaining to the watchdog timer, alarm and battery status. The M48T212A also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As V CC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
M48T212A
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TSLD (2) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 sec Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -55 to 125 260 -0.3 to 4.6 -0.3 to 4.6 20 1 Unit C C C V V mA W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes (1)
Mode Deselect Write 3.0V to 3.6V Read Read Deselect Deselect VSO to VPFD (min) (2) VSO (2) VIL VIL X X VIL VIH X X VIH VIH X X DOUT High-Z High-Z High-Z Active Active CMOS Standby Battery Back-Up VCC E VIH VIL G X X W X VIL DQ7-DQ0 High-Z DIN Power Standby Active
Note: 1. X = VIH or VIL. 2. VSO = Battery Back-up Switchover Voltage. (See Table 7 for details).
Table 4. Truth Table for SRAM Bank Select (1)
Mode Select 3.0V to 3.6V Deselect Deselect Deselect VSO to VPFD (min) (2) VSO (2) Low High X X High X X X High High High High Low High High High Active Standby CMOS Standby Battery Back-Up VCC EX Low A Low E1CON Low E2CON High Power Active
Note: 1. X = VIH or VIL. 2. VSO = Battery Back-up Switchover Voltage. (See Table 7 for details).
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M48T212A
Figure 3. Hardware Hookup
A0-A18
3.3V
A0-A3 VCC VCCSW
MOTOROLA MTD20P06HDL
A0-Axx VOUT 0.1F VCC CMOS SRAM E
0.1F
1N5817 (1) A E EX W G
M48T212A
E1CON Note 2 E2CON
WDI RSTIN1 RSTIN2 DQ0-DQ7 VCAP SuperCap Supply VSS XI RST IRQ/FT X0 32 kHz Crystal E VCC CMOS SRAM A0-Axx
AI03049
Note: 1. See description in Power Supply Decoupling and Undershoot Protection. 2. Traces connecting E1CON and E2CON to external SRAM should be as short as possible.
Figure 4. AC Testing Load Circuit (3,4)
Table 5. AC Measurement Conditions
Input Rise and Fall Times 5ns 0 to 3V 1.5V Input Pulse Voltages Input and Output Timing Ref. Voltages
DEVICE UNDER TEST
645
Note that Output Hi-Z is defined as the point where data is no longer driven.
CL = 100pF or 5pF (1) CL = 30 pF (2) 1.75V
CL includes JIG capacitance
AI03239
Note: 1. DQ0-DQ7 2. E1CON and E2 CON 3. Excluding open-drain output pins
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M48T212A
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT (2) Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. Outputs deselected.
Table 7. DC Characteristics (TA = 0 to 70C; VCC = 3V to 3.6V)
Symbol ILI
(1,2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Battery Current OSC ON Battery Current OSC OFF Input Low Voltage Input High Voltage Output Low Voltage
Test Condition 0V VIN VCC 0V VOUT VCC Outputs Open E = VIH E = VCC -0.2
Min
Typ
Max 1 1
Unit A A mA mA mA nA nA V V V V V
ILO (1) ICC ICC1 ICC2 IBAT VIL VIH VOL VOH VOHB (4) IOUT1 (5) IOUT2 VPFD VSO VBAT VCAP
Note: 1. 2. 3. 4.
4
10 3 2
575
800 100
-0.3 2.0 IOL = 2.1mA IOL = 10mA IOH = -1.0mA IOUT2 = -1.0A VOUT1 > VCC -0.3 VOUT2 > VBAT -0.3 2.7 2.9 VPFD -100mV 3.0 VCC 2.4 2.0
0.8 VCC + 0.3 0.4 0.4
Output Low Voltage (open drain) (3) Output High Voltage VOH Battery Back-up VOUT Current (Active) VOUT Current (Battery Back-up) Power-fail Deselect Voltage Battery Back-up Switchover Voltage Battery Voltage Capacitor Voltage (6)
3.6 70 100 3.0
V mA A V V V V
Outputs deselected. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. For IRQ/FT & RST pins (Open Drain). Conditioned outputs (E1CON - E2CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will reduce battery life. 5. External SRAM must match TIMEKEEPER Controller chip VCC specification. 6. When fully charged.
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M48T212A
Figure 5. Power Down/Up AC Waveform
VCC VPFD (max) VPFD (min) VSO tF tFB tRB tR tREC
INPUTS
VALID
DON'T CARE
VALID
HIGH-Z OUTPUTS VALID VALID
RST
VCCSW
AI02638
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70C)
Symbol tF tFB tR tREC tRB Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VPFD (max) to RST High VSS to VPFD (min) VCC Rise Time Min 300 150 10 40 5 200 Max Unit s s s ms s
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M48T212A
Table 9. Chip Enable Control and Bank Select Characteristics (TA = 0 to 70C)
M48T212A Symbol Parameter Min tEXPD tAPD EX to E1CON or E2CON (Low or High) A to E1CON or E2CON (Low or High) -85 Max 15 15 ns ns Unit
Figure 6. Chip Enable Control and Bank Select Timing
EX tEXPD A tEXPD E1CON tAPD
E2CON
AI02639
Table 10. Read Mode Characteristics (TA = 0 to 70C)
M48T212A Symbol Parameter Min tAVAV tAVQV tELQV tGLQV tELQX (1) tGLQX (1) tEHQZ (1) tGHQZ (1) tAXQX
Note: 1. CL = 5pF
-85 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
85 85 85 35 5 0 25 25 5
ns ns ns ns ns ns ns ns ns
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M48T212A
Address Decoding The M48T212A accommodates 4 address lines (A3-A0) which allow access to the sixteen bytes of the TIMEKEEPER clock registers. All TIMEKEEPER registers reside in the controller chip itself. All TIMEKEEPER registers are accessed by enabling E (Chip Enable). READ MODE The M48T212A executes a read cycle whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the address inputs (A3-A0) defines which one of the on-chip TIMEKEEPER registers is to be accessed. When the address presented to the M48T212A is in the range of 0h-Fh, one of the on-board TIMEKEEPER registers is accessed and valid data will be available to the eight data output drivers within tAVQV after the address input signal is stable, providing that the E and G access times are also satisfied. If they are not, then data access must be measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the address access time. When EX input is low, an external SRAM location will be selected. Note: Care should be taken to avoid taking both E and EX low simultaneously to avoid bus contention.
Table 11. Write Mode AC Characteristics (TA = 0 to 70C)
M48T212A Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1,2) tAVWH tAVEH tWHQX (1,2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output High-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 65 65 5 85 0 0 55 60 0 0 30 30 0 0 25 -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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M48T212A
Figure 7. Read Cycle Timing: RTC Control Signals
READ tAVAV ADDRESS tELQV E tELQX G tGLQV
READ tAVAV
WRITE tAVAV
tAVQV
tAVWL
tWHAX
tWLWH W
tGLQX
tAXQX tGHQZ
DQ7-DQ0
DATA OUT VALID
DATA OUT VALID
DATA IN VALID
AI02640
Figure 8. Write Cycle Timing: RTC Control Signals
WRITE tAVAV ADDRESS tAVEH tAVEL E tELEH
WRITE tAVAV
READ tAVAV
tAVWH tEHAX tWHAX tAVQV
tGLQV G tEHDX tAVWL W tEHQZ DQ0-DQ7
DATA OUT VALID
tWLWH
tWHQX
tWLQZ
tDVEH
DATA IN VALID
tDVWH
DATA IN VALID
tWHDX
DATA OUT VALID
AI02641
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M48T212A
Table 12. Alarm Repeat Modes
RPT5 1 1 1 1 1 0 RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
Figure 9. Alarm Interrupt Reset Waveforms
A0-A3
1h
ADDRESS 0h
Fh
ACTIVE FLAG BIT
IRQ/FT HIGH-Z
AI03021
WRITE MODE The M48T212A is in the Write Mode whenever W (Write Enable) and E (Chip Enable) are in a low state after the address inputs are stable. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. When E is low during the write, one of the onboard TIMEKEEPER registers will be selected and data will be written into the device. When EX is low (and E is high) an external SRAM location is selected. Note: Care should be taken to avoid taking both E and EX low simultaneously to avoid bus contention.
DATA RETENTION MODE With valid VCC applied, the M48T212A can be accessed as described above with read or write cycles. Should the supply voltage decay, the M48T212A will automatically deselect, write protecting itself (and any external SRAM) when V CC falls between V PFD (max) and V PFD (min). This is accomplished by internally inhibiting access to the clock registers via the E signal. At this time, the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing E1CON and E2CON to a high level. This level is within 0.2V of the VBAT. E1CON and E2CON will remain at this level as long as VCC remains at an out-of tolerance condition. When V CC falls below the level of the battery (VBAT), power input is switched from the VCC pin to the battery and the clock registers and external SRAM are maintained from the attached battery supply. All outputs become high impedance. The VOUT pin is capable of supplying 100A of current to the attached memory with less than 0.3V drop under this condition. On power up, when V CC returns to a nominal value, write protection continues for 200ms (max) by inhibiting E1CON or E2CON.
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M48T212A
Table 13. TIMEKEEPER Register Map
Address D7 Fh Eh Dh Ch Bh Ah 9h 8h 7h 6h 5h 4h 3h 2h 1h 0h
Keys:
D6
D5
D4
D3
D2 Year
D1
D0
Function/Range BCD Format Year Month Date Day Hour Min Sec Control 00-99 01-12 01-31 01-7 00-23 00-59 00-59
10 Years 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 R BMB4 0 RPT5 0 0 0 FT 0 0 0 10M 10 Date 0 0
Month Date: Day of Month Day of Week Hours (24 Hour Format) Minutes Seconds Calibration
10 Hours 10 Minutes 10 Seconds S BMB3 ABE BMB2 Al 10M BMB1
BMB0
RB1
RB0
Watchdog A Month A Date A Hour A Min A Sec Century 01-12 01-31 00-23 00-59 00-59 00-99
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds 100 Year
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds 1000 Year
WDF
AF
Y
BL
Y
Y
Y
Y
Flag
S = Sign Bit FT = Frequency Test Bit R = Read Bit W = Write Bit ST = Stop Bit 0 = Must be set to zero BL = Battery Low Flag BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag RB0-RB1 = Watchdog Resolution Bits WDS = Watchdog Steering Bit ABE = Alarm in Battery Back-Up Mode Enable Bit RPT1-RPT5 = Alarm Repeat Mode Bits WDF = Watchdog flag AF = Alarm flag Y = '1' or '0'
The RST signal also remains active during this time (see Figure 5). Note: Most low power SRAMs on the market today can be used with the M48T212A TIMEKEEPER Controller. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M48T212A and SRAMs to be Don't Care once VCC falls below VPFD(min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M48T212A to determine the total current requirements for data retention. The available battery capacity can then be divided by this current to determine the amount of data retention available. For a further more detailed review of lifetime calculations, please see Application Note AN1012.
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M48T212A
TIMEKEEPER REGISTERS The M48T212A offers 16 internal registers which contain TIMEKEEPER, Alarm, Watchdog, Flag, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT TM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Flags Registers store data in Binary Format. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the Control Register (8h). As long as a 1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second after the READ bit is reset to a '0'. Setting the Clock Bit D7 of the Control Register (8h) is the WRITE bit. Setting the WRITE bit to a 1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 13). Resetting the WRITE bit to a 0' then transfers the values of all time registers (Fh-9h, 1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur one second later. Note: Upon power-up following a power failure, the READ bit will automatically be set to a 1'. This will prevent the clock from updating the TIMEKEEPER registers, and will allow the user to read the exact time of the power-down event. Resetting the READ Bit to a 0' will allow the clock to update these registers with the current time. The WRITE Bit will be reset to a 0' upon powerup. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at Bit D7 within the Seconds Register (9h). Setting it to a '1' stops the oscillator. When reset to a '0', the M48T212A oscillator starts within one second. Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). SETTING ALARM CLOCK REGISTERS Address locations 6h-2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M48T212A is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 12 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. The IRQ/FT output is cleared by a read to the Flags register as shown in Figure 9. A subsequent read of the Flags register will reset the Alarm Flag (D6; Register 0h). The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T212A was in the deselect mode during power-up. Figure 10 illustrates the back-up mode alarm timing.
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M48T212A
Figure 10. Back-Up Mode Alarm Waveforms
tREC VCC VPFD (max) VPFD (min)
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT HIGH-Z HIGH-Z
AI03622
WATCHDOG TIMER The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 7h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The amount of timeout is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds). If the processor does not reset the timer within the specified period, the M48T212A sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a ` 0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a ` 1', the watchdog will output a negative pulse on the RST pin for 40 to 200 ms. The Watchdog register and the FT bit will reset to a ` 0' at the end of a Watchdog time-out when the WDS bit is set to a ` 1'.
The watchdog timer can be reset by two methods: 1. a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI) or 2. the microprocessor can perform a write of the Watchdog Register. The time-out period then starts over. The WDI pin should be tied to VSS if not used. The watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A read of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0h). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied.
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M48T212A
VCC SWITCH OUTPUT Vccsw output goes low when VOUT switches to VCC turning on a customer supplied P-Channel MOSFET (see Figure 3). The Motorola MTD20P06HDL is recommended. This MOSFET in turn connects V OUT to a separate supply when the current requirement is greater than IOUT1 (see Table 7). This output may also be used simply to indicate the status of the internal battery switchover comparator, which controls the source (VCC or battery) of the V OUT output. POWER-ON RESET The M48T212A continuously monitors V CC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on powerup for 40 to 200ms after VCC passes VPFD. The RST pin is an open drain output and an appropriate pull-up resistor to V CC should be chosen to control rise time. Note: If the RST output is fed back into either of the RSTIN inputs (for a microprocessor with a bidirectional reset) then a 1k (max) pull-up resistor is recommended. Reset Inputs (RSTIN1 & RSTIN2) The M48T212A provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 14 and Figure 12 illustrate the AC reset characteristics of this function. During the time RST is enabled (tR1HRH & tR2HRH), the Reset Inputs are ignored. Note: RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100K resistor. Calibrating the Clock The M48T212A is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25C. The oscillation rate of crystals changes with temperature. The M48T212A design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 8h. These bits can be set to represent any value between 0 and
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31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T212A may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER Calibration. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 9h) is '0', the Frequency Test bit (FT, D6 of Ch) is '1', the Alarm Flag Enable bit (AFE, D7 of 6h) is '0', and the Watchdog Steering bit (WDS, D7 of 7h) is '1' or the Watchdog Register (7h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-up.
M48T212A
Table 14. Reset AC Characteristics (TA = 0 to 70C; VCC = 3V to 3.6V)
Symbol tR1 (1) tR2 (2) tR1HRH (3) tR2HRH (3) Parameter RSTIN1 Low to RSTIN1 High RSTIN2 Low to RSTIN2 High RSTIN1 High to RST High RSTIN2 High to RST High Min 200 100 40 40 200 200 Max Unit ns ms ms ms
Note: 1. Pulse width less than 50ns will result in no RESET (for noise immunity). 2. Pulse width less than 20ms will result in no RESET (for noise immunity). 3. CL = 5pF (see Figure 4).
Table 15. Crystal Electrical Characteristics (Externally Supplied)
Symbol fO RS CL Description Resonant Frequency Series Resistance Load Capacitance Min Typ 32,768 50 12.5 70 Max Unit kHz k pF
Note: Load capacitors are integrated within the M48T212A. Circuit board layout considerations for the 32kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. ST recommends the KDS DT-38 Tuning Fork Type quartz crystal for all temperature operations. KDS can be contacted at 913-491-6825 or at http://www.kdsj.co.jp for forther information on this crystal type.
BATTERY LOW WARNING The M48T212A automatically performs battery voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24 hours. The Battery Low (BL) bit, Bit D4 of Flags Register 0h, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal Vcc is supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the battery should be replaced. The battery should be replaced with VCC powering the device to avoid data loss. The M48T212A only monitors the battery when a nominal Vcc is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. Note: Battery Low warning is only valid when using a 3V button cell battery. Use a super capacitor for back-up supply causes the BL flag to be invalid. INITIAL POWER-ON DEFAULTS Upon application of power to the device, the following register bits are set to a '0' state: WDS, BMB0-BMB4, RB0-RB1, AFE, ABE, W and FT (See Table 16).
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M48T212A
Figure 11. Calibration Waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
Figure 12. RSTIN1 & RSTIN2 Timing Waveforms
RSTIN1 tR1 RSTIN2 tR2 RST (1) tR1HRH tR2HRH
AI02642
Note: 1. With pull-up resistor.
Table 16. Default Values
Condition Initial Power-up (Battery Attach for SNAPHAT) (2) RESET (3) Power-down (4) Subsequent Power-up
Note: 1. 2. 3. 4.
W 0 0 0 0
R 0 0 1 1
FT 0 0 0 0
AFE 0 0 1 0
ABE 0 0 1 0
WATCHDOG Register (1) 0 0 0 0
WDS, BMB0-BMB4, RB0, RB1. State of other control bits undefined. State of other control bits remains unchanged. Assuming these bits set to `1' prior to power-down.
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M48T212A
POWER SUPPLY DECOUPLING AND UNDERSHOOT PROTECTION Note: ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V CC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 13. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48T212A
Table 17. Ordering Information Scheme
Example: Device Type M48T Supply Voltage and Write Protect Voltage 212A = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V Speed -85 = 85ns Package MH = SOH44 Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Shipping Method for SOIC blank = Tubes TR = Tape & Reel M48T212A -85 MH 1 TR
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 18. Revision History
Date October 1999 First Issue SNAPHAT Battery & Crystal removed Hardware Hookup scheme changed (Figure 3) Back-Up Mode Alarm Waveforms changed (Figure 10) Default Values Table added (Table 16) SOH44 package silhouette, mechanical drawings and mechanical data changed (Figure 14) Revision Details
03/01/00
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M48T212A
Table 19. SOH44 - 44 lead Plastic Small Outline SNAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e H L N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 11.51 0.41 0 44 0.10 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.500 0.050 8 inches
Figure 14. SOH44 - 44 lead Plastic Small Outline SNAPHAT, Package Outline
A2 B e
A C CP
D
N
E
H A1 L
1 SOH-C
Drawing is not to scale.
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M48T212A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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